Regression Test Summary:

Test output can be found at '/glade/scratch/kavulich/REGTEST/workdir/ifort_20170524_00:13:09'

EXPERIMENT PAROPT CPU_MPI CPU_OMP JOB STATUS WALLTIME(S) RESULT
4denvar_large_conus dmpar 48 1 done 146 ok
UNTAR_ENS_DATA done 43
WRFDA_4DENVAR done 103
ASR_airs dmpar 16 1 done 216 ok
3DVAR done 216
ASR_prepbufr dm+sm 16 1 done 106 ok
3DVAR done 106
ASR_prepbufr dmpar 16 1 done 72 ok
3DVAR done 72
afwa_t7_ssmi dmpar 4 1 done 28 ok
3DVAR done 28
afwa_t7_ssmi serial 1 1 done 69 ok
3DVAR done 69
afwa_t7_ssmi_32 dmpar 4 1 done 41 ok
3DVAR done 41
afwa_t7_ssmi_32 serial 1 1 done 59 ok
3DVAR done 59
amsr2 dmpar 16 1 done 204 ok
3DVAR done 204
cv3_guo dmpar 7 1 done 25 ok
3DVAR done 25
cv3_guo serial 1 1 done 61 ok
3DVAR done 61
cv3_guo_32 dmpar 9 1 done 26 ok
3DVAR done 26
cv3_guo_32 serial 1 1 done 77 ok
3DVAR done 77
cwb_ascii dm+sm 4 4 done 22 ok
3DVAR done 22
cwb_ascii dmpar 4 1 done 17 ok
3DVAR done 17
cwb_ascii serial 1 1 done 37 ok
3DVAR done 37
cwb_ascii smpar 1 4 done 24 ok
3DVAR done 24
cwb_ascii_outerloop_rizvi dmpar 4 1 done 39 ok
3DVAR done 39
cwb_ascii_outerloop_rizvi serial 1 1 done 71 ok
3DVAR done 71
cwb_ascii_thinning dm+sm 4 4 done 47 ok
3DVAR done 47
cwb_ascii_thinning dmpar 4 1 done 40 ok
3DVAR done 40
cwb_ascii_thinning serial 1 1 done 36 ok
3DVAR done 36
cwb_ascii_thinning smpar 1 4 done 38 ok
3DVAR done 38
cycle_ne_blizzard dmpar 16 1 done 136 ok
WRFDA_init done 16
UPDATE_BC_LAT done 5
WRF done 53
UPDATE_BC_LOW done 3
WRFDA_final done 59
cycle_sene_hires dmpar 16 1 done 276 ok
WRFDA_init done 11
UPDATE_BC_LAT done 6
WRF done 188
UPDATE_BC_LOW done 3
WRFDA_final done 68
dual_res_hybrid dm+sm 16 1 done 90 ok
UNTAR_ENS_DATA done 7
WRFDA_3DENVAR done 83
dual_res_hybrid dmpar 16 1 done 54 ok
UNTAR_ENS_DATA done 4
WRFDA_3DENVAR done 50
iasi_kavulich dmpar 16 1 done 202 ok
3DVAR done 202
lat_lon_outerloops dmpar 16 1 done 212 ok
OBSPROC done 53
3DVAR done 159
multirad_pacific dmpar 32 1 done 207 ok
3DVAR done 207
multirad_pacific_nc4 dmpar 32 1 done 213 ok
3DVAR done 213
outerloop_ztd_bench_guo dm+sm 1 1 done 17 ok
3DVAR done 17
outerloop_ztd_bench_guo dmpar 1 1 done 15 ok
3DVAR done 15
outerloop_ztd_bench_guo serial 1 1 done 7 ok
3DVAR done 7
outerloop_ztd_bench_guo smpar 1 1 done 7 ok
3DVAR done 7
radar_cv7 dmpar 8 1 done 359 ok
GENBE done 295
3DVAR done 64
radar_meixu dmpar 8 1 done 27 ok
3DVAR done 27
radar_meixu serial 1 1 done 47 ok
3DVAR done 47
radar_null_echo dmpar 16 1 done 112 ok
3DVAR done 112
realtime_hybrid dmpar 32 1 done 259 ok
ENS_MEAN_VARI done 13
ENS_PERT done 143
VERT_LOC done 3
WRFDA_3DENVAR done 100
seviri_varbc dmpar 16 1 done 222 ok
VARBC done 116
3DVAR done 106
sfc_assi_2_outerloop_guo dmpar 16 1 done 51 ok
3DVAR done 51
sfc_assi_2_outerloop_guo serial 1 1 done 171 ok
3DVAR done 171
t44_liuz dm+sm 2 2 done 15 ok
3DVAR done 15
t44_liuz dmpar 2 1 done 19 ok
3DVAR done 19
t44_liuz serial 1 1 done 13 ok
3DVAR done 13
t44_liuz smpar 1 2 done 11 ok
3DVAR done 11
t44_prepbufr dmpar 8 1 done 28 ok
3DVAR done 28
t44_prepbufr serial 1 1 done 49 ok
3DVAR done 49
tut_xinzhang_fgat dmpar 16 1 done 157 ok
OBSPROC done 107
FGAT done 50
tut_xinzhang_obsproc dmpar 16 1 done 135 ok
OBSPROC done 72
3DVAR done 63
tut_xinzhang_rttov_genbe dmpar 10 1 done 128 ok
GENBE done 65
3DVAR done 63
wind_sd dm+sm 16 1 done 56 ok
3DVAR done 56
wind_sd dmpar 16 1 done 36 ok
3DVAR done 36
wind_sd serial 1 1 done 160 ok
3DVAR done 160